1. Technical Field
The present disclosure generally relates to devices and methods for controlling accesses to memories, be they stand-alone memories or memories embedded in electronic circuits comprising other functions such as, for example, circuits for controlling digital data transmission networks or image processing circuits.
2. Description of the Related Art
Generally, electronic circuits have a significant data storage capacity. Such a capacity is reached with large memories formed of several memory blocks for physical or logical reasons. For example, such memories are of SRAM (Static Random-Access Memory) or DRAM (Dynamic Access Memory) type only. A memory controller enables the other functions of the electronic circuit to see all the memory blocks as a single memory, in terms of address.
Generally, the memory blocks have a single-port architecture. In other words, as seen from the other electronic circuit functions, a single-port block can only perform one read operation or one write operation at the same time. This memory block architecture enables avoiding too complex memory architectures, or architectures consuming too much circuit surface area. However, it may sometimes be desirable for some functions of the electronic circuit to simultaneously perform a read operation and a write operation, with no address constraint.
A known solution to this problem is to use dual-port memories capable of performing two operations at the same time. The disadvantages of dual-port memories are their low densities and high access times. Such memories are thus poorly adapted to the storage of large data words.
Another known solution to this problem is to use memory blocks performing operations at a clock frequency at least double that of the external circuit. A disadvantage of this solution is that memory blocks withstanding a high frequency must be available and that such blocks take up a large surface area. Another disadvantage of such a solution is that the circuit must be designed to be able to operate with several clock frequencies.
Another known solution to this problem is to delay conflicting operations, such as a simultaneous reading from and writing into the same memory block. A disadvantage of this solution is that an additional memory space must be available to temporarily store the data to be written which have caused the conflict. To be protected against the worst case, for which each address of a memory block will be successively read, and then written, this additional memory space must have the same size as the initial memory. Another disadvantage of this solution is that the processing (writing) of the data stored in the additional memory space may block the access to the memory for a given time period.